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1/26 january 2003 M41T256Y 256 kbit (32k x 8) serial rtc features summary n 5v operating voltage n serial interface supports extended i 2 c bus addressing (400 khz) n automatic switch-over and d eselect circuitry n power-fail deselect voltages: C M41T256Y: v cc = 4.5 to 5.5v; v pfd = 4.2 < v pfd < 4.5v n counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year n programmable software clock calibration n 32,752 bytes of general purpose ram n microprocessor power-on reset n holds microprocessor in reset until supply voltage reaches stable operating level n automatic address-incrementing n tamper indication circuit with time- stamp n sleep mode function n packaging includes a 44-lead soic and snaphat ? top (to be ordered separately) n soic package provides direct connection for a snaphat ? top which contains the battery and crystal figure 1. 44-pin, hatless soic package figure 2. 44-pin soic package 44 1 so44 (mt) 44 1 soh44 (mh) snaphat (sh) crystal/battery
M41T256Y 2/26 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 logic diagram (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal names (table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 44-pin soic connections (mt) (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 block diagram (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc and ac measurement conditions (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ac testing input/output waveforms (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc characteristics (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 crystal electrical characteristics (externally supplied) (table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 serial bus data transfer sequence (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 acknowledgement sequence (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bus timing requirements sequence (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ac characteristics (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 slave address location (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read mode sequence (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 alternate read mode sequence (figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write mode sequence (figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power down/up mode ac waveforms (figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power down/up ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/26 M41T256Y clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 timekeeper? register map (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 tamper indication circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 tamper event time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 preferred power-on/battery attach defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 preferred default values (table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 crystal accuracy across temperature (figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 clock calibration (figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 snaphat? battery table (table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M41T256Y 4/26 summary description the M41T256Y serial timek eeper ? sram is a low power 256 kbit static cmos sram organized as 32k words by 8 bits. a built-in 32.768 khz os- cillator (external crystal controlled) and 8 bytes of the sram (see figure 9, page 17) are used for the clock/calendar function and are configured in bina- ry coded decimal (bcd) format. addresses and data are transferred serially via a two line, bi-directional i 2 c interface. the built-in address register is incremented automatically af- ter each write or read data byte. the M41T256Y has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power fail- ure occurs. the energy needed to sustain the sram and clock operations can be supplied by a lithium button-cell supply when a power failure oc- curs. functions available to the user include a non-volatile, time-of-day clock/calendar, and pow- er-on reset. the eight clock address locations contain the year, month, date, day, hour, minute, second, and tenths/hundredths of seconds in 24- hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the first clock address loca- tion (7ff8h) stores the clock software calibration settings as well as the write clock bit. the M41T256Y is supplied in a 44-lead soic snaphat ? package (mh - which integrates both crystal and battery in a single snaphat top) or a 44-pin hatless soic (mt). the 44-pin, 330mil soic provides sockets with gold-plated contacts at both ends for direct connection to a separate snaphat housing containing the battery and crystal. the unique design allows the snaphat battery/crystal package to be mounted on top of the soic package after the completion of the sur- face-mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is also keyed to prevent reverse insertion. the 44-pin soic and crystal/battery packages are shipped separately in plastic, anti-static tubes or in tape & reel form. for the 44-lead soic, the battery/crys- tal package (e.g., snaphat) part number is m4txx-br12sh (see table 12, page 21). caution: do not place the snaphat battery/crys- tal top in conductive foam, as this will drain the lith- ium, button-cell battery. figure 3. logic diagram note: 1. for 44-pin snaphat (mt) package only. table 1. signal names note: 1. for 44-pin snaphat (mt) package only. ai04754b scl v cc M41T256Y v ss sda tp ft rst v bat (1) xi (1) xo (1) xi (1) oscillator input xo (1) oscillator output ft frequency test (open drain) rst reset output (open drain) scl serial clock input sda serial data input/output v cc supply voltage v bat (1) battery supply voltage v ss ground tp tamper input
5/26 M41T256Y figure 4. 44-pin soic connections (mt) note: no function (nf) must be tied to v ss . figure 5. 44-pin soic (mh - snaphat) figure 6. block diagram note: 1. open drain output 22 44 43 1 M41T256Y 10 2 5 6 7 8 9 11 12 13 14 15 21 40 39 36 35 34 33 32 31 30 29 28 3 4 38 37 42 41 16 17 18 19 20 27 26 25 24 23 xo xi nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf tp nc nf rst sda v ss v ss nc v ss v cc nc ft nc nc nf scl nc nc nc bat+ ai04755b 22 44 43 1 M41T256Y 10 2 5 6 7 8 9 11 12 13 14 15 21 40 39 36 35 34 33 32 31 30 29 28 3 4 38 37 42 41 16 17 18 19 20 27 26 25 24 23 nc nc nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf nf tp nc nf rst sda v ss v ss nc v ss v cc nc ft nc nc nf scl nc nc nc nc ai07022 ai04759 compare v pfd = 4.38v v cc compare v so = v bat power v bl = 2.5v bl compare crystal i 2 c interface real time clock calendar 32,752 bytes user ram rtc & calibration tamper bit sda scl por rst (1) tp v bat 32khz oscillator ft (1) pull-up to chip v cc
M41T256Y 6/26 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 t o 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t stg storage temperature (v cc off, oscillator off) snaphat ? C40 to 85 c soic C55 to 125 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to v cc + 0.3 v v cc supply voltage C0.3 to 7.0 v i o output current 20 ma p d power dissipation 1 w
7/26 M41T256Y dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. dc and ac measurement conditions figure 7. ac testing input/output waveforms table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter M41T256Y v cc supply voltage 4.5 to 5.5v ambient operating temperature C25 to 70c load capacitance (c l ) 100pf input rise and fall times 50ns input pulse voltages 0.2v cc to 0.8v cc input and output timing ref. voltages 0.3v cc to 0.7v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance 7 pf input capacitance (tamper pin) 1000 pf c io (3) input / output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
M41T256Y 8/26 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = C25 to 70c; v cc = 4.5 to 5.5v (except where noted). 2. outputs deselected. 3. for rst and ft pin (open drain). table 6. crystal electrical characteristics (externally supplied) note: 1. stmicroelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial temperature operations. kds can be contacted at kouhou@kdsj.co.jp or ht- tp://www.kdsj.co.jp for further information on this crystal type. 2. load capacitors are integrated within the M41T256Y. circuit board layout considerations for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account. sym parameter test condition (1) min typ max unit i bat battery current osc on t a = 25c, v cc = 0v, v bat = 3.0v 1.5 1.9 a battery current osc off 1.0 1.4 a i cc1 supply current f = 400khz 1.4 3.0 ma i cc2 supply current (standby) scl, sda = v cc C 0.3v 1.0 2.5 ma i li input leakage current 0v v in v cc 1 a i lo (2) output leakage current 0v v out v cc 1 a v ih input high voltage 0.7v cc v cc + 0.3 v v ihb input high voltage in battery back- up for tamper pin v bat C vdiode v bat v v il input low voltage C0.3 0.3v cc v v bat battery voltage 2.5 3.5 v v oh output high voltage v cc + 0.3 v v ol output low voltage i ol = 3.0ma 0.4 v output low voltage (open drain) (3) i ol = 10ma 0.4 v v pfd power fail deselect 4.20 4.50 v v so battery back-up switchover v bat v r sw switch resistance on tamper pin 500 w symbol parameter (1,2) typ min max unit f 0 resonant frequency 32.768 khz r s series resistance 35 k w c l load capacitance 12.5 pf
9/26 M41T256Y operating modes the M41T256Y clock operates as a slave device on the serial bus. access is obtained by imple- menting a start condition followed by the correct slave address (d0h). the 256k bytes contained in the device can then be accessed sequentially in the following order: 0-7fef = general purpose ram 7ff0-7ff6 = reserved 7ff7h = tenths/hundredths register 7ff8h = control register 7ff9h = seconds register 7ffah = minutes register 7ffbh = hour register 7ffch = tamper/day register 7ffdh = date register 7ffeh = month register 7fffh = year register the M41T256Y clock continually monitors v cc for an out-of tolerance condition. should v cc fall be- low v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. when v cc falls below v so , the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd plus t rec . for more information on battery storage life refer to application note an1012. 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bi-direction- al data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: C data transfer may be initiated only when the bus is not busy. C during data transfer, the data line must remain stable whenever the clock line is high. C changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition a device that gives out a message is called transmitter, the receiving device that gets the message is called receiver. the device that controls the message is called master. the de- vices that are controlled by the master are called slaves. acknowledge. each byte of eight bits is followed by one acknowledge clock pulse. this acknowl- edge clock pulse is a low level put on the bus by the receiver whereas the master generates an ex- tra acknowledge related clock pulse. a slave re- ceiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition.
M41T256Y 10/26 figure 8. serial bus data transfer sequence figure 9. acknowledgement sequence ai04756 (sda) data (scl) clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
11/26 M41T256Y figure 10. bus timing requirements sequence table 7. ac characteristics note: 1. valid for ambient operating temperature: t a = C25 to 70c; v cc = 4.5 to 5.5v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. symbol parameter (1) min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t f sda and scl fall time 300 ns t hd:dat data hold time 0 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat (2) data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
M41T256Y 12/26 read mode in this mode the master reads the M41T256Y slave after setting the slave address (see figure 11, page 12). following the write mode control bit (r/w =0) and the acknowledge bit, the byte ad- dresses a(0) and a(1) are written to the on-chip address pointer (msb of address byte a(0) is a dont care). next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master trans- mitter becomes the master receiver. the data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the M41T256Y slave transmitter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to an+2. this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter (see figure 12, page 13). note: address pointer will wrap around from max- imum address to minimum address if consecutive read or write cycles are performed. an alternate read mode may also be implement- ed whereby the master reads the M41T256Y slave without first writing to the (volatile) address point- er. the first address that is read is the last one stored in the pointer (see figure 13, page 13). write mode in this mode the master transmitter transmits to the M41T256Y slave receiver. bus protocol is shown in figure figure 14, page 13. following the start condition and slave address, a logic '0' (r/ w =0) is placed on the bus and indicates to the ad- dressed device that byte addresses a(0) and a(1) will follow and is to be written to the on-chip ad- dress pointer (msb of address byte a(0) is a dont care). the data byte to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowl- edge bit. the M41T256Y slave receiver will send an acknowledge bit to the master transmitter after it has received the slave address (see figure 11, page 12) and again after it has received each ad- dress byte. figure 11. slave address location note: the most significant bit is sent first. ai00602 r/w slave address start a 01000 11 msb lsb
13/26 M41T256Y figure 12. read mode sequence figure 13. alternate read mode sequence figure 14. write mode sequence ai04760 bus activity: ack s ack ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+x byte address (0) byte address (1) slave address s start r/w slave address ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address ai04761 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+x byte address (0) slave address byte address (1)
M41T256Y 14/26 data retention mode with valid v cc applied, the M41T256Y can be ac- cessed as described above with read or write cycles. should the supply voltage decay, the M41T256Y will automatically deselect, write pro- tecting itself when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally inhibiting access to the clock registers. at this time, the reset pin (rst ) is driven active and will remain active until v cc returns to nominal levels. when v cc falls below the battery back-up switchover voltage (v so ), power input is switched from the v cc pin to the external battery and the clock registers and sram are maintained from the attached battery supply. all outputs become high impedance. on power up, when v cc returns to a nominal value, write protec- tion continues for t rec . the rst signal also re- mains active during this time (see figure 15, page 15). for a further more detailed review of lifetime calcu- lations, please see application note an1012. sleep mode in order to minimize the battery current draw while in storage, the M41T256Y provides the user with a battery sleep mode, which disconnects the ram memory array from the external lithium battery normally used to provide non-volatile operation in the absence of v cc . this can significantly extend the lifetime of the battery, when non-volatile oper- ation is not needed. note: the sleep mode will remove power from the ram array only and not affect the data retention of the timekeeper registers (7ff0h through 7fffh - this includes the calibration register). the sleep mode (slp) bit located in register 7ff8h (d6), must be set to a '1' by the user while the device is powered by v cc . this will arm the sleep mode latch, but not actually disconnect the ram array from power until the next power-down cycle. this protects the user from immediate data loss in the event he inadvertently sets the slp bit. once v cc falls below v so (v bat ), the sleep mode circuit will be engaged and the ram array will be isolated from the battery, resulting in both a lower battery current, and a loss of ram data. note: upon initial battery attach or initial power application without the battery, the state of the slp bit will be undetermined. therefore, the slp bit should be initialized to '0' by the user. additional current reduction can be achieved by setting the stop (st) bit in register 7ff9h (d7), turning off the clock oscillator. this combination will result in the longest possible battery life, but also loss of time and data. when the device is again powered-up, the user should first read the slp bit to determine if the device is currently in sleep mode, then reset the bit to '0' in order to dis- able the sleep mode (this will not be automatical- ly taken care of during the power-up). note: see an1570, M41T256Y sleep mode function for more information on sleep mode and battery lifetimes.
15/26 M41T256Y figure 15. power down/up mode ac waveforms table 8. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = C25 to 70c; v cc = 4.5 to 5.5v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. at 25c, using a br2330 li battery. this drops to 7.2 years when using the m4t32-br12sh with the oscillator running. symbol parameter (1) min typ max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec power up deselect time 40 200 ms t dr expected data retention time (osc on, sleep mode off) 15 (4) years ai04757 v cc inputs (per control input) outputs don't care high-z tf tfb tr trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec rst
M41T256Y 16/26 clock operation year, month, and date are contained in the last three registers of the timekeeper ? register map (see table 9). bits d0 through d2 of the next register contain the day (day of week). finally, there are the registers containing the seconds, minutes, and hours, respectively. the first clock register is the control register (this is described in the clock calibration section). the nine clock registers may be read one byte at a time, or in a sequential block. the control reg- ister (address location 7ff8h) may be accessed independently. provision has been made to as- sure that a clock update does not occur while any of the nine clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a transi- tion of data during the read. reading the clock the nine byte clock register (see table 9) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (7ff9h to 7fffh). the update will re- sume either due to a stop condition or when the pointer increments to a ram address. this prevents reading data in transition. the timekeeper ? cells in the register map are only data registers and not actual clock counters, so updating the registers can be halted without dis- turbing the clock itself. setting the clock bit d7 of the control register (7ff8h) is the write clock bit. setting the write clock bit to a '1' will al- low the user to write the desired day, date, and time data in 24-hour bcd format. resetting the write clock bit to a '0' then transfers the values of all time registers (7ff8h-7fffh) to the actual clock counters and resets the internal divider (or clock) chain. note: the tenths/hundredths of seconds regis- ter will automatically be reset to zero when the write clock bit is set. other register bits such as ft, teb, and st may be written without setting the wc bit. in such cas- es, the clock data will be undisturbed and will re- tain their previous values. stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit (st) is the most significant bit of the seconds reg- ister. setting it to '1' stops the oscillator. setting it to '0' restarts the oscillator in approximately one second.
17/26 M41T256Y table 9. timekeeper ? register map keys: s = sign bit ft = frequency test bit st = stop bit wc = write clock bit x = '1' or '0' bl = battery low flag (read only bit) tb = tamper bit (read only bit) teb = tamper enable bit 0 = must be set to '0' slp = sleep mode bit note: 7ff0h through 7ff6h are invalid addresses and when read will return arbitrary data. address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 7fffh 10 years year year 00-99 7ffeh 0 0 0 10m month month 01-12 7ffdh 0 0 10 date date: day of month date 01-31 7ffch bl ft teb tb 0 day of week tamper/day 0-1/01-07 7ffbh 0 0 10 hours hours (24 hour format) hours 00-23 7ffah 0 10 minutes minutes minutes 00-59 7ff9h st 10 seconds seconds seconds 00-59 7ff8h wc slp s calibration control 7ff7h 0.1 seconds 0.01 seconds seconds 00-99 7ff6h x x x x x x x x reserved 7ff5h x x x x x x x x reserved 7ff4h x x x x x x x x reserved 7ff3h x x x x x x x x reserved 7ff2h x x x x x x x x reserved 7ff1h x x x x x x x x reserved 7ff0h x x x x x x x x reserved
M41T256Y 18/26 power-on reset the M41T256Y continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power- up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time. tamper indication circuit the M41T256Y provides an independent input pin, the tamper pin (tp) which can be used to monitor a signal which can result in the setting of the tamper bit (tb) if the tamper enable bit (teb) is set to a '1.' the tamper pin is triggered by being connected to v cc /v bat through an external switch. this switch is normally open in the application, allowing the pin to be floating (internally latched to v ss when teb is set). when this switch is closed (connecting the pin to v cc /v bat ), the tamper bit will be immedi- ately set. this allows the user to determine if the device has been physically moved or tampered with. the tamper bit is a read only bit and is re- set only by taking the tamper pin to ground and resetting the tamper enable bit to '0.' this function operates both under normal power, and in battery back-up. if the switch closes during a power-down condition, the bit will still be set cor- rectly. note: upon initial battery attach or initial power application without the battery, the state of teb (and tb) will be undetermined. therefore teb must be initialized to a '0.' tamper event time-stamp if a tamper occurs, not only will the tamper bit be set, but the event will also automatically be time- stamped. this is accomplished by freezing the normal update of the clock registers (7ff7h through 7fffh) immediately following a tamper event. thus, when tampering occurs, the user may first read the time registers to determine exactly when the tamper event occurred, then re-enable the clock update to the current time (and reset the tamper bit,tb) by resetting the tamper enable bit (teb). the time update will then resume, and after either a stop condition or incrementing the address pointer to a ram address and back, the clock can be read to determine the current time. note: the tamper bit (tb) must always be set to '0' in order to read the current time. calibrating the clock the M41T256Y is driven by a quartz controlled os- cillator with a nominal frequency of 32,768 hz. the devices are tested not exceed +/C35 ppm (parts per million) oscillator frequency error at 25 o c, which equates to about +/C1.53 minutes per month. when the calibration circuit is properly em- ployed, accuracy improves to better than +1/C2 ppm at 25c. the oscillation rate of crystals changes with tem- perature (see figure 16, page 20). therefore, the M41T256Y design employs periodic counter cor- rection. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 17, page 20. the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value load- ed into the five calibration bits found in the control register. adding counts speeds the clock up, sub- tracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register (7ff8h). these bits can be set to represent any value be- tween 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates nega- tive calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or C2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month.
19/26 M41T256Y two methods are available for ascertaining how much calibration a given M41T256Y may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934: tim ekeeper calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that ac- cesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the ft pin. the pin will toggle at 512hz, when the stop bit (st) is '0,' and the frequency test bit (ft) is '1.' any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscilla- tor frequency error, requiring a C10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output fre- quency. the ft pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500 to 10k resistor is recommended in order to control the rise time. the ft bit is cleared on pow- er-down. battery low warning the M41T256Y automatically performs battery voltage monitoring upon power-up. the battery low (bl) bit, bit d7 of day register, will be assert- ed if the battery voltage is found to be less than ap- proximately 2.5v. the bl bit will remain asserted until completion of battery replacement and sub- sequent battery low monitoring tests, during the next power-up sequence. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. the battery may be replaced while v cc is applied to the device. the M41T256Y only monitors the battery when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. preferred power-on/battery attach defaults see table 10, below. table 10. preferred default values note: 1. x = undetermined; uc = unchanged condition wc teb (1) tb (1) ft st (1) slp (1) battery attach or initial power-up 0 x x 0 x x power-cycling (with battery) 0 uc uc 0 uc uc
M41T256Y 20/26 figure 16. crystal accuracy across temperature figure 17. clock calibration ai00999 C160 0 10203040506070 frequency (ppm) temperature c 80 C10 C20 C30 C40 C100 C120 C140 C40 C60 C80 20 0 C20 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ai00594b normal positive calibration negative calibration
21/26 M41T256Y part numbering table 11. ordering information scheme note: 1. the soic package (soh44) requires the battery package (snaphat ? ) which is ordered separately under the part number m4txx-br12sh in plastic tube or m4txx-br12shtr in tape & reel form. caution : do not place the snaphat battery package m4txx-br12sh in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 12. snaphat ? battery table example: m41t 256y mt 7 tr device type m41t supply voltage and write protect voltage 256y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v package mt = 44-lead, hatless soic mh (1) = soh44 temperature range 7 = C25 to 70c shipping method for soic blank = tubes tr = tape & reel part number description package m4t32-br12sh lithium battery (120mah) snaphat sh
M41T256Y 22/26 package mechanical information figure 18. soh44 C 44-lead plastic, hatless, small package outline note: drawing is not to scale. table 13. soh44 C 44-lead plastic, hatless, small package mechanical data symbol millimeters inches typ min max typ min max a 3.05 0 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 0.81 C C 0.032 C C h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n44 44 cp 0.10 0.004 soh-c e n d c l a1 a 1 h a cp be a2
23/26 M41T256Y figure 19. soh44 C 44-lead plastic small outline, snaphat, package outline note: drawing is not to scale. table 14. soh44 C 44-lead plastic small outline, snaphat, package mechanical data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 0.81 C C 0.032 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n44 44 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
M41T256Y 24/26 figure 20. sh C 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 15. sh C 4-pin snaphat housing for 120mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
25/26 M41T256Y revision history table 16. document revision history date rev. # revision details february 2002 1.0 first issue 04/26/02 1.1 addition of tamper event time-stamp text 05/31/02 1.2 add sleep mode, 44-pin with snaphat package (figure 2, 5, 19, 20; table 1, 2, 11, 12, 14, 15) 07/03/02 1.3 modify crystal electrical characteristics table footnotes (table 6) 07/12/02 1.4 added programmable sleep mode information to document (figure 3, 4, 5, 6; table 9, 10) 07/29/02 1.5 add hatless to package description (figure 1, 18 and table 11, 13) 12/20/02 2.0 i cc characteristics changed (table 5); document promoted to datasheet 01/04/03 2.1 add v ol value (table 5)
M41T256Y 26/26 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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